In many semiconductor devices, multi-layer metal interconnections are provided by separating the metal interconnection layers with insulating layers. The different metal interconnection layers can be connected using contact (or via) holes through the insulating layers.
FIGS. 1A through 1D illustrate steps of a method of forming contact holes through an insulating layer according to the prior art. As shown in FIG. 1A, a device isolation region 12 is formed on a semiconductor substrate 10 to define active and inactive regions of the substrate. An insulating layer 14 is formed and patterned to provide a contact hole 15 therethrough. A metal interconnection layer 16 is then deposited on the insulating layer 14 filling the contact hole 15. The metal interconnection layer 16 provides a lower metal interconnection layer.
An insulating layer 18 is then formed on the metal interconnection layer 16 and on the insulating layer 14 as shown in FIG. 1B. A second metal interconnection layer can later be formed on the insulating layer 18 so that the first and second insulating layers can be separated by the insulating layer 18. A photoresist layer 20 is deposited and patterned on the insulating layer 18 to provide an etch mask defining a contact hole to be etched through the insulating layer 18. A wet etch step is performed using the patterned photoresist layer 20 as a mask thus isotropically etching the insulating layer 18 as shown in FIG. 1C. The undercut a of the photoresist layer 20 may, however, be generated during this wet etch step.
A dry etching step can then be used to complete the contact hole 22 through the insulating layer 18 thus exposing portions of the metal interconnection layer 16 as shown in FIG. 1D. Again, the patterned photoresist layer 20 is used as an etch mask during the dry etch step. The photoresist layer 20 can then be removed, and a second metal interconnection layer can be formed on the insulating layer 18. Accordingly, the contact holes 22 can be used to provide interconnections between the first and second metal interconnection layers.
The undercut a illustrated in FIGS. 1C and 1D may occur, however, because of poor adhesion between the photoresist layer 20 and the insulating layer 18. For example, an etchant used during the wet etch step may penetrate along an interface between the photoresist layer and the insulating layer causing voids along the interface therebetween. Accordingly, even though the contact hole 22 is formed using wet and dry etching steps, the thickness of the insulating layer 18 may be significantly reduced adjacent the contact hole 22. An undesired step may thus be generated on the insulating layer 18 thereby degrading the insulation provided by the insulating layer 18 between upper and lower interconnection layers.